The present invention has broad applicability to any situation where data is being communicated between two different clock domains. However, the present invention will be described, for convenience, in the context of communication within a computer. For example, the Intel.RTM. PCI bus provides a bus connection between one or more master applications, an Intel processor, and main memory. The PCI bus allows for a master "dispatcher" to communicate application-writes to main memory across the PCI bus. The PCI bus permits the master application to drive the address of a subsequent master application operation as soon as the occurrence of the clock immediately following the last data transfer of a master application write request. In order to facilitate such communication, the master "dispatcher" is generally synchronous to the PCI clock so that the PCI finite state machine is able to load the address of a new master request in the cycle immediately following a previous write data cycle. In a modular PCI bus design, the PCI finite state machine and the PCI bus driver logic must be tied to an industry standard 33 or the 66 MHz PCI clock. This clock frequency is referred to as the read side clock for the read side domain. However, it is very desirable to have the master dispatcher or master cycle requester not be required to run at the same clock frequency as the PCI bus read side clock. Specifically, it is very undesirable to place a particular frequency constraint on the clocks running the various applications on the write side domain. It is preferred that the various applications on the write side be able to operate at their maximum clock speeds. Examples of write side domain applications which should be permitted to operate at their preferred maximum clock speed are ethernet controllers, graphics controllers, and disk controllers.
Additionally, because getting on and off the PCI bus in order to facilitate a data transfer is very time consuming, it is desired that any data transfer be as efficient as possible. This is a particular problem for data transferred from a write side clock domain to a read side clock domain (the PCI bus), because the handshake acknowledge signals must be communicated back and forth between these two clock domains.